module crc32_d8_rec_02(
		input	wire		resetb,
		input	wire		sclk,
	
		input	wire		dsin,
		input	wire	[7:0]	din,
		
		output	reg		crc32_cal_end,
		output	reg		crc32_error
		);
		
//***********************************************************************
reg		dsin_t,data_last;
reg	[2:0]	d_count;
reg	[7:0]	d;
wire	[31:0]	c;
reg	[31:0]	crc32_value;

//***********************************************************************
always@(posedge sclk or negedge resetb)
	if(resetb==0)
		d_count<=0;
	else if (dsin==0)
		d_count<=0;
	else if (d_count[2]==0)
		d_count<=d_count+1;

always@(d_count or din)
	if(d_count[2]==0)
		d<=~din;
	else
		d<=din;

assign c = crc32_value;

always@(posedge sclk)
	if (dsin==0)
		crc32_value <= 32'h00000000;
	else
	begin
		crc32_value[31] <= c[29]^c[23];
		crc32_value[30] <= c[31]^c[28]^c[22];
		crc32_value[29] <= c[31]^c[30]^c[27]^c[21];
		crc32_value[28] <= c[30]^c[29]^c[26]^c[20];
		crc32_value[27] <= c[31]^c[29]^c[28]^c[25]^c[19];
		crc32_value[26] <= c[30]^c[28]^c[27]^c[24]^c[18];
		crc32_value[25] <= c[27]^c[26]^c[17];
		crc32_value[24] <= c[31]^c[26]^c[25]^c[16];
		crc32_value[23] <= c[30]^c[25]^c[24]^c[15];
		crc32_value[22] <= c[24]^c[14];
		crc32_value[21] <= c[29]^c[13];
		crc32_value[20] <= c[28]^c[12];
		crc32_value[19] <= c[31]^c[27]^c[11];
		crc32_value[18] <= c[31]^c[30]^c[26]^c[10];
		crc32_value[17] <= c[30]^c[29]^c[25]^c[9];
		crc32_value[16] <= c[29]^c[28]^c[24]^c[8];
		crc32_value[15] <= c[31]^c[29]^c[28]^c[27]^c[7];
		crc32_value[14] <= c[31]^c[30]^c[28]^c[27]^c[26]^c[6];
		crc32_value[13] <= c[31]^c[30]^c[29]^c[27]^c[26]^c[25]^c[5];
		crc32_value[12] <= c[30]^c[29]^c[28]^c[26]^c[25]^c[24]^c[4];
		crc32_value[11] <= c[28]^c[27]^c[25]^c[24]^c[3];
		crc32_value[10] <= c[29]^c[27]^c[26]^c[24]^c[2];
		crc32_value[9]  <= c[29]^c[28]^c[26]^c[25]^c[1];
		crc32_value[8]  <= c[28]^c[27]^c[25]^c[24]^c[0];
		
		crc32_value[7]  <= c[31]^c[29]^c[27]^c[26]^c[24]^d[0];
		crc32_value[6]  <= c[31]^c[30]^c[29]^c[28]^c[26]^c[25]^d[1];
		crc32_value[5]  <= c[31]^c[30]^c[29]^c[28]^c[27]^c[25]^c[24]^d[2];
		crc32_value[4]  <= c[30]^c[28]^c[27]^c[26]^c[24]^d[3];
		crc32_value[3]  <= c[31]^c[27]^c[26]^c[25]^d[4];
		crc32_value[2]  <= c[31]^c[30]^c[26]^c[25]^c[24]^d[5];
		crc32_value[1]  <= c[31]^c[30]^c[25]^c[24]^d[6];
		crc32_value[0]  <= c[30]^c[24]^d[7];
	end

always@(posedge sclk)
	dsin_t<=dsin;

always@(dsin or dsin_t)
	if (dsin==0 && dsin_t==1)
		data_last<=1;
	else
		data_last<=0;

always@(posedge sclk)
	crc32_cal_end<=data_last;

always@(posedge sclk or negedge resetb)
	if (resetb==0)
		crc32_error<=0;
	else if (data_last==1) begin
		if (crc32_value==32'hffffffff)
			crc32_error<=0;
		else
			crc32_error<=1;
		end

endmodule